In one embodiment, an integrated circuit includes multiple I/O banks, each bank having multiple I/O-ESD tiles, each tile having one or more I/O circuits and electrostatic discharge (ESD) protection circuitry for the one or more I/O circuits in the tile. The ESD circuitry for one tile includes at least one RC-triggered clamp, whose resistance is provided by a resistor shared by one or more other RC-triggered clamps in one or more other tiles of the same bank and whose capacitance is provided by a combination of distributed capacitors, one for each of those two or more RC-triggered clamps. Each tile may have multiple instances of such RC-triggered clamps providing ESD protection for different (e.g., power supply and/or bus) nodes. The shared resistors are variable to allow different instances of the same ESD circuitry design to be implemented with the same time constant for different banks having different numbers of tiles.