A split gate memory device, a semiconductor device and a manufacturing method thereof are provided. In the split gate memory device, an erasing gate is further disposed, wherein the easing gate and a control gate are respectively disposed on two sides of a floating gate. Thus, an erase operation is implemented by the erasing gate instead of the control gate. Accordingly, electric potential applied to the control gate is reduced. Therefore, hot-electron effect in channel region may be avoided, and performance degradation of the memory caused by the hot-electron effect may be avoided as well. Furthermore, as electric potential applied to the control gate is reduced, a gate oxide layer underneath the control gate may be thinner. Accordingly, manufacturing processes of the control gate and the gate oxide layer and that of the gate and the gate oxide layer of a logic transistor in a periphery circuit may be compatible.