Invention Grant
- Patent Title: Shallow trench isolation area having buried capacitor
- Patent Title (中): 浅沟槽隔离区有埋电容
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Application No.: US14521302Application Date: 2014-10-22
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Publication No.: US09536872B2Publication Date: 2017-01-03
- Inventor: Hartmud Terletzki
- Applicant: Infineon Technologies AG
- Applicant Address: DE Neubiberg
- Assignee: Infineon Technologies AG
- Current Assignee: Infineon Technologies AG
- Current Assignee Address: DE Neubiberg
- Agency: Slater Matsil, LLP
- Main IPC: H01L27/06
- IPC: H01L27/06 ; H01L27/02 ; H01L49/02 ; H01L21/762 ; H01L21/8234 ; H01L29/06 ; H01L29/66 ; H01L29/94

Abstract:
A semiconductor chip includes a substrate including a surface, an active transistor region and a substrate contact region formed on the substrate, a shallow trench isolation (STI) area formed in the surface and disposed at least partially between the active transistor region and the substrate contact region, and at least one capacitor at least partially buried in the STI area.
Public/Granted literature
- US20150041949A1 Shallow Trench Isolation Area Having Buried Capacitor Public/Granted day:2015-02-12
Information query
IPC分类: