Invention Grant
- Patent Title: Method of manufacturing through silicon via stacked structure
- Patent Title (中): 通过堆叠结构制造硅的方法
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Application No.: US14963252Application Date: 2015-12-09
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Publication No.: US09536785B2Publication Date: 2017-01-03
- Inventor: Po-Chun Lin
- Applicant: NANYA TECHNOLOGY CORP.
- Applicant Address: TW Taoyuan
- Assignee: NANYA TECHNOLOGY CORP.
- Current Assignee: NANYA TECHNOLOGY CORP.
- Current Assignee Address: TW Taoyuan
- Agent Winston Hsu; Scott Margo
- Main IPC: H01L21/48
- IPC: H01L21/48 ; H01L21/768 ; H01L25/04 ; H01L23/48 ; H01L25/065 ; H01L25/11 ; H01L25/075 ; H01L25/07
Abstract:
A method of manufacturing through silicon via stacked structures. A plurality of substrates is provided. At least one tapered hole is formed on one surface of each substrate. Each tapered hole is filled up with a tapered through silicon via. A recessed portion is formed on the wider end of each tapered through silicon via. A part of the substrate is removed until the narrower end of each tapered through silicon via protrudes from the other surface of the substrate. The substrates is stacked one after another by fitting and jointing the narrower end of each tapered through silicon via on one substrate into a corresponding recessed portion of the tapered through silicon via of another substrate.
Public/Granted literature
- US20160093532A1 METHOD OF MANUFACTURING THROUGH SILICON VIA STACKED STRUCTURE Public/Granted day:2016-03-31
Information query
IPC分类:
