Invention Grant
US09536626B2 Memory subsystem I/O performance based on in-system empirical testing
有权
基于系统内部测试的内存子系统I / O性能
- Patent Title: Memory subsystem I/O performance based on in-system empirical testing
- Patent Title (中): 基于系统内部测试的内存子系统I / O性能
-
Application No.: US13763511Application Date: 2013-02-08
-
Publication No.: US09536626B2Publication Date: 2017-01-03
- Inventor: Theodore Z. Schoenborn , Christopher P. Mozak
- Applicant: Theodore Z. Schoenborn , Christopher P. Mozak
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Main IPC: G11C29/06
- IPC: G11C29/06 ; G11C29/56 ; G11C29/04

Abstract:
A memory subsystem empirically tests performance parameters of I/O with a memory device. Based on the empirical testing, the memory subsystem can set the performance parameters specific to the system in which the memory subsystem is included. A test system performs the testing. For each of multiple different settings for multiple different I/O circuit parameters, the test system sets a value for each I/O circuit parameter, generates test traffic to stress test the memory device with the parameter value(s), and measures an operating margin for the I/O performance characteristic. The test system further executes a search function to determine values for each I/O circuit parameter at which the operating margin meets a minimum threshold and performance of at least one of the I/O circuit parameters is increased. The memory subsystem sets runtime values for the I/O circuit parameters based on the search function.
Public/Granted literature
- US20140229666A1 MEMORY SUBSYSTEM I/O PERFORMANCE BASED ON IN-SYSTEM EMPIRICAL TESTING Public/Granted day:2014-08-14
Information query