A memory system has an array of split gate non-volatile NVM cells that are in program sectors and the program sectors make up one or more erase sectors. The control gate of cells in a program sector are physically connected. A program/erase circuit programs a selected program sector by applying a programming signal to the control gates of the split gate memory cells of the selected program sector while applying a non-programming signal to the control gates of program sectors not selected for programming, that erases an erase sector comprising a plurality of the program sectors by contemporaneously applying an erase voltage to the control gates of the split gate NVM cells of the erase sector, wherein during the applying the programming signal, the program/erase circuit applies a source voltage to the sources of each of the split gate NVM cells of the erase sector.