Invention Grant
- Patent Title: Nonvolatile logic gate device
- Patent Title (中): 非易失逻辑门装置
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Application No.: US14400950Application Date: 2013-05-15
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Publication No.: US09536584B2Publication Date: 2017-01-03
- Inventor: Ryusuke Nebashi , Noboru Sakimura , Yukihide Tsuji , Ayuka Tada , Tadahiko Sugibayashi , Takahiro Hanyu , Tetsuo Endoh , Hideo Ohno
- Applicant: NEC CORPORATION , TOHOKU UNIVERSITY
- Applicant Address: JP Tokyo JP Miyagi
- Assignee: NEC CORPORATION,TOHOKU UNIVERSITY
- Current Assignee: NEC CORPORATION,TOHOKU UNIVERSITY
- Current Assignee Address: JP Tokyo JP Miyagi
- Agency: Sughrue Mion, PLLC
- Priority: JP2012-132412 20120611
- International Application: PCT/JP2013/064138 WO 20130515
- International Announcement: WO2013/187193 WO 20131219
- Main IPC: G11C11/00
- IPC: G11C11/00 ; G11C11/16 ; H03K19/18 ; H03K3/356 ; G11C13/00

Abstract:
A nonvolatile logic gate device is configured to include a resistive network of a memory structure in which at least three nonvolatile resistive elements are connected, a reference resistive network as a reference resistance providing a tolerance of the memory structure to a resistance value of the resistive network of the memory structure, a writing part operable to selectively write or rewrite a value of each of the nonvolatile resistive elements in the resistive network into a maximum or a minimum corresponding to a logical value to be read when data are stored into the resistive network, and a logic circuit structure operable to use, as a logical value of the memory structure, a value obtained by comparison between the resistance value of the resistive network and the resistance value of the reference resistive network.
Public/Granted literature
- US20150138877A1 NONVOLATILE LOGIC GATE DEVICE Public/Granted day:2015-05-21
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