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US09536032B2 Method and system of layout placement based on multilayer gridlines 有权
基于多层网格线的布局布局方法和系统

Method and system of layout placement based on multilayer gridlines
Abstract:
A method of forming a layout design for fabricating an integrated circuit is disclosed. The method includes identifying a line pattern of a first set of grid lines with respect to a second set of grid lines within a region of the layout design; and placing a k-th standard cell layout of the K standard cell layouts at the region of the layout design if the line pattern is determined to match a k-th predetermined line pattern of K predetermined line patterns. K is an integer equal to or greater than two, and k is an order index ranging from 1 to K. The region of the layout design is sized to fit one of K different standard cell layouts corresponding to a same standard cell functionality.
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