Invention Grant
US09536032B2 Method and system of layout placement based on multilayer gridlines
有权
基于多层网格线的布局布局方法和系统
- Patent Title: Method and system of layout placement based on multilayer gridlines
- Patent Title (中): 基于多层网格线的布局布局方法和系统
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Application No.: US14554958Application Date: 2014-11-26
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Publication No.: US09536032B2Publication Date: 2017-01-03
- Inventor: Ting-Wei Chiang , Li-Chun Tien , Hui-Zhong Zhuang , Zhe-Wei Jiang
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Applicant Address: TW
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW
- Agency: Hauptman Ham, LLP
- Main IPC: G06F17/50
- IPC: G06F17/50 ; H03K19/02 ; H01L27/02

Abstract:
A method of forming a layout design for fabricating an integrated circuit is disclosed. The method includes identifying a line pattern of a first set of grid lines with respect to a second set of grid lines within a region of the layout design; and placing a k-th standard cell layout of the K standard cell layouts at the region of the layout design if the line pattern is determined to match a k-th predetermined line pattern of K predetermined line patterns. K is an integer equal to or greater than two, and k is an order index ranging from 1 to K. The region of the layout design is sized to fit one of K different standard cell layouts corresponding to a same standard cell functionality.
Public/Granted literature
- US20160147926A1 METHOD AND SYSTEM OF FORMING LAYOUT DESIGN Public/Granted day:2016-05-26
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