A circuit design checker receives a circuit design. The circuit design can include a first set of one or more logic components in a first clock domain and a second set of one or more logic components in a second clock domain. The clock domain checker identifies a first subset of the second set of one or more logic components that receive one or more asynchronous clock domain crossings. The circuit design is traversed to determine whether a subset of the one or more asynchronous clock domain crossings does not pass through a signal having an attribute indicating that the signal is intended to be part of the one or more asynchronous clock domain crossings. If such a crossing exists, an error is indicated for the circuit design.