Invention Grant
US09535849B2 IOMMU using two-level address translation for I/O and computation offload devices on a peripheral interconnect
有权
IOMMU在外设互连上使用I / O和计算卸载设备的两级地址转换
- Patent Title: IOMMU using two-level address translation for I/O and computation offload devices on a peripheral interconnect
- Patent Title (中): IOMMU在外设互连上使用I / O和计算卸载设备的两级地址转换
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Application No.: US12508890Application Date: 2009-07-24
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Publication No.: US09535849B2Publication Date: 2017-01-03
- Inventor: Andrew G. Kegel , Mark D. Hummel , Stephen D. Glaser
- Applicant: Andrew G. Kegel , Mark D. Hummel , Stephen D. Glaser
- Applicant Address: US CA Sunnyvale
- Assignee: ADVANCED MICRO DEVICES, INC.
- Current Assignee: ADVANCED MICRO DEVICES, INC.
- Current Assignee Address: US CA Sunnyvale
- Agency: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.
- Agent Erik A. Heter
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F12/10 ; G06F3/06 ; G06F12/08 ; G06F12/02 ; G06F12/06
Abstract:
An IOMMU for controlling requests by an I/O device to a system memory of a computer system includes control logic and a cache memory. The control logic may translate an address received in a request from the I/O device. If the request includes a transaction layer protocol (TLP) packet with a process address space identifier (PASID) prefix, the control logic may perform a two-level guest translation. Accordingly, the control logic may access a set of guest page tables to translate the address received in the request. A pointer in a last guest page table points to a first table in a set of nested page tables. The control logic may use the pointer in a last guest page table to access the set of nested page tables to obtain a system physical address (SPA) that corresponds to a physical page in the system memory. The cache memory stores completed translations.
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