Invention Grant
US09439270B2 Digital communication receiver interface circuit for line-pair with duty cycle imbalance compensation 有权
数字通信接收机接口电路,用于线路对与占空比不平衡补偿

  • Patent Title: Digital communication receiver interface circuit for line-pair with duty cycle imbalance compensation
  • Patent Title (中): 数字通信接收机接口电路,用于线路对与占空比不平衡补偿
  • Application No.: US14436716
    Application Date: 2013-10-11
  • Publication No.: US09439270B2
    Publication Date: 2016-09-06
  • Inventor: Stefan-Cristian Rezeanu
  • Applicant: KONINKLIJKE PHILIPS N.V.
  • Applicant Address: NL Eindhoven
  • Assignee: KONINKLIJKE PHILIPS N.V.
  • Current Assignee: KONINKLIJKE PHILIPS N.V.
  • Current Assignee Address: NL Eindhoven
  • Agent Meenakshy Chakravorty
  • International Application: PCT/IB2013/059314 WO 20131011
  • International Announcement: WO2014/060922 WO 20140424
  • Main IPC: H05B37/00
  • IPC: H05B37/00 H05B37/02
Digital communication receiver interface circuit for line-pair with duty cycle imbalance compensation
Abstract:
A circuit (200) includes: a diode bridge (210) having polarity-independent input terminals for coupling to a DALI bus, and having positive and negative output terminals, wherein the diode bridge receives a receive signal from the DALI bus; a galvanic isolation device (220) having an input for receiving the receive signal from the diode bridge, and an output for outputting the receive signal galvanically isolated from the diode bridge and the DALI bus; a receive signal threshold reference device (235) for setting a threshold voltage for the galvanic isolation device to respond to the receive signal; an amplifier (280) for receiving the galvanically isolated receive signal from the galvanic isolation device and outputting a binary digital signal via a low pass filter (290); and a first duty cycle control device (230, 270) for adjusting the timing of rising edges of the galvanically isolated receive signal with respect to its falling edges.
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