Invention Grant
- Patent Title: LLR computation device and error correction decoding device
- Patent Title (中): LLR计算装置和纠错解码装置
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Application No.: US14343305Application Date: 2012-10-05
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Publication No.: US09438377B2Publication Date: 2016-09-06
- Inventor: Kenya Sugihara , Wataru Matsumoto
- Applicant: Kenya Sugihara , Wataru Matsumoto
- Applicant Address: JP Tokyo
- Assignee: Mitsubishi Electric Corporation
- Current Assignee: Mitsubishi Electric Corporation
- Current Assignee Address: JP Tokyo
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2011-259068 20111128
- International Application: PCT/JP2012/075992 WO 20121005
- International Announcement: WO2013/080668 WO 20130606
- Main IPC: H03M13/00
- IPC: H03M13/00 ; H04L1/00 ; H04L25/06 ; H03M13/11 ; H04L27/38 ; H04L25/03

Abstract:
A two-reference-point-pair determining unit 101 determines two reference point pairs by selecting two transmission symbol points with their LLR computation target bit being 0 and two transmission symbol points with their LLR computation target bit being 1. An LLR computation unit 113 assigns weights to the two LLRs calculated for the two reference point pairs, respectively, followed by adding them, and further adds to the addition result a correction term that may be zero sometimes, thus computing LLR for the two reference point pairs.
Public/Granted literature
- US20140229805A1 LLR COMPUTATION DEVICE AND ERROR CORRECTION DECODING DEVICE Public/Granted day:2014-08-14
Information query
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