Invention Grant
US09437705B2 Method of manufacturing a spacer for dual gate electronic memory cell and associated electronic memory cell
有权
制造用于双门电子存储单元和相关联的电子存储单元的间隔件的方法
- Patent Title: Method of manufacturing a spacer for dual gate electronic memory cell and associated electronic memory cell
- Patent Title (中): 制造用于双门电子存储单元和相关联的电子存储单元的间隔件的方法
-
Application No.: US14341171Application Date: 2014-07-25
-
Publication No.: US09437705B2Publication Date: 2016-09-06
- Inventor: Anthony De Luca , Christelle Charpin-Nicolle
- Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
- Applicant Address: FR Paris
- Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
- Current Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
- Current Assignee Address: FR Paris
- Agency: Pillsbury Winthrop Shaw Pittman LLP
- Priority: FR1357379 20130726
- Main IPC: H01L29/51
- IPC: H01L29/51 ; H01L21/28 ; H01L21/3213 ; H01L29/423 ; H01L29/40 ; H01L29/66 ; H01L29/792 ; H01L21/311 ; H01L21/00
Abstract:
A method of manufacturing a spacer for an electronic memory including a substrate; a first gate structure; a stack including a plurality of layers whereof at least one of the layers is able to store electric charges, the method including depositing a spacer material layer, at least on the area covered by the stack; ion beam machining the spacer material layer, the ion beam machining being carried out with controlled stopping so as to preserve a residual portion of the thickness of the spacer material layer covering the stack; plasma etching the residual portion of the thickness of the spacer material layer.
Public/Granted literature
Information query
IPC分类:
