Invention Grant
- Patent Title: Method for manufacturing semiconductor device having a multilayer interconnection
- Patent Title (中): 具有多层互连的半导体器件的制造方法
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Application No.: US14518389Application Date: 2014-10-20
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Publication No.: US09437568B2Publication Date: 2016-09-06
- Inventor: Atsuko Kawasaki
- Applicant: Kabushiki Kaisha Toshiba
- Applicant Address: JP Minato-ku
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Minato-ku
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2013-256070 20131211
- Main IPC: H01L21/4763
- IPC: H01L21/4763 ; H01L21/44 ; H01L21/76 ; H01L21/302 ; H01L21/461 ; H01L23/00 ; H01L25/065 ; H01L25/00
Abstract:
Certain embodiments provide a method for manufacturing a semiconductor device including forming a first interconnection layer having a first conductive layer and a first insulating layer which are exposed from a surface of the first interconnection layer, forming a second interconnection layer having a second conductive layer and a second insulating layer which are exposed from a surface of the second interconnection layer, forming a first non-bonded surface on the surface of the first insulating layer by making a partial area of the surface of the first insulating layer lower than the surface of the first conductive layer, the partial area containing surroundings of the first conductive layer, and connecting the surface of the first conductive layer and the surface of the second conductive layer and bonding the surface of the first insulating layer excluding the first non-bonded surface and the surface of the second insulating layer.
Public/Granted literature
- US20150162294A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE Public/Granted day:2015-06-11
Information query
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