- Patent Title: Semiconductor device having features to prevent reverse engineering
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Application No.: US14504868Application Date: 2014-10-02
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Publication No.: US09437555B2Publication Date: 2016-09-06
- Inventor: William Eli Thacker, III
- Applicant: Verisiti, Inc.
- Applicant Address: US NC Sanford
- Assignee: Verisiti, Inc.
- Current Assignee: Verisiti, Inc.
- Current Assignee Address: US NC Sanford
- Main IPC: H01L29/788
- IPC: H01L29/788 ; H01L23/00 ; H01L27/06 ; H01L49/02 ; H01L29/49 ; H01L27/02 ; H01L27/115 ; H01L27/105 ; H01L29/66 ; H01L23/522
Abstract:
It is desirable to design and manufacture electronic chips that are resistant to modern reverse engineering techniques. Disclosed is a method and device that allows for the design of chips that are difficult to reverse engineer using modern teardown techniques. The disclosed device uses devices having the same geometry but different voltage levels to create different logic devices. Alternatively, the disclosed uses devices having different geometries and the same operating characteristics. Also disclosed is a method of designing a chip using these devices.
Public/Granted literature
- US20160099219A1 Semiconductor Device Having Features to Prevent Reverse Engineering Public/Granted day:2016-04-07
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