Invention Grant
- Patent Title: Additional etching to increase via contact area
- Patent Title (中): 附加蚀刻以通过接触面积增加
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Application No.: US14484589Application Date: 2014-09-12
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Publication No.: US09437540B2Publication Date: 2016-09-06
- Inventor: Pei-Yi Lin , Chung-Ju Lee , Shau-Lin Shue
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: H01L23/522
- IPC: H01L23/522 ; H01L23/528 ; H01L21/3213 ; H01L21/311 ; H01L21/768 ; H01L21/321 ; H01L23/532

Abstract:
An integrated circuit structure includes a dielectric layer, and a conductive line in the dielectric layer. The conductive line has a first top surface and a second top surface lower than the first top surface, and a sidewall connecting the first top surface to the second top surface. A via includes a portion overlying the second top surface of the conductive line. The via is electrically coupled to the conductive line through the second top surface and the sidewall of the conductive line.
Public/Granted literature
- US20160079161A1 ADDITIONAL ETCHING TO INCREASE VIA CONTACT AREA Public/Granted day:2016-03-17
Information query
IPC分类: