Invention Grant
- Patent Title: Method for manufacturing electrical connections in a semiconductor device and the semiconductor device
- Patent Title (中): 用于制造半导体器件和半导体器件中的电连接的方法
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Application No.: US14630171Application Date: 2015-02-24
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Publication No.: US09437527B2Publication Date: 2016-09-06
- Inventor: Takeshi Yokoyama
- Applicant: FUJI ELECTRIC CO., LTD.
- Applicant Address: JP Kawasaki-Shi
- Assignee: FUJI ELECTRIC CO., LTD.
- Current Assignee: FUJI ELECTRIC CO., LTD.
- Current Assignee Address: JP Kawasaki-Shi
- Agency: Rabin & Berdo, P.C.
- Priority: JP2014-075581 20140401; JP2014-147096 20140717
- Main IPC: H01L23/495
- IPC: H01L23/495 ; H01L23/02 ; H01L23/48 ; H01L23/52 ; H01L23/12 ; H01L23/28 ; H01L23/00 ; H01L23/057

Abstract:
A resin casing is insert-molded while clamp protrusions of clamp portions formed in bonding portions of lead terminals are put between an upper mold and a lower mold. An insulating substrate which has a wiring pattern mounted with semiconductor elements is fitted into an opening portion of the resin casing and adhesively bonded to the resin casing. Electric connection between the semiconductor elements and the bonding portions of the lead terminals and between the wiring pattern on the insulating substrate and the bonding portions of the lead terminals is made by bonding wires. Thus, it is possible to provide a method for manufacturing a semiconductor device and the semiconductor device, in which stress applied to lead terminals of a lead frame formed by insert molding can be suppressed, and wire bonding properties and reliability can be improved even when the thickness of each of the lead terminals is reduced.
Public/Granted literature
- US20150279752A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND THE SEMICONDUCTOR DEVICE Public/Granted day:2015-10-01
Information query
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