Invention Grant
- Patent Title: Method and structure for wafer-level packaging
- Patent Title (中): 晶圆级封装的方法和结构
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Application No.: US14964869Application Date: 2015-12-10
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Publication No.: US09437511B2Publication Date: 2016-09-06
- Inventor: Jiangen Shi
- Applicant: NANTONG FUJITSU MICROELECTRONICS CO., LTD.
- Applicant Address: CN Nantong
- Assignee: NANTONG FUJITSU MICROELECTRONICS CO., LTD.
- Current Assignee: NANTONG FUJITSU MICROELECTRONICS CO., LTD.
- Current Assignee Address: CN Nantong
- Agency: Anova Law Group, PLLC
- Priority: CN201410762885 20141211
- Main IPC: H01L23/544
- IPC: H01L23/544 ; H01L23/31 ; H01L21/82 ; H01L21/56 ; H01L21/768 ; H01L23/00 ; H01L23/532

Abstract:
A method for wafer-level packaging includes providing a semiconductor wafer having a plurality of semiconductor chips connected by connection stems in the wafer. The method further includes forming a plurality of through holes in the connections stems; forming a protective layer covering the wafer with a plurality of positions for planting soldering balls exposed. The protective layer includes an upper protective layer formed on a top side of the wafer, a lower protective layer formed on a back side of the wafer, and a plurality of middle protective layers formed in the through holes. The upper protective layer is connected to the lower protective layer through the plurality of the middle protective layers. The method also includes forming soldering balls on the positions for planting soldering balls and finally, forming a plurality of packaged individual semiconductor chip structures by cutting the wafer along the connection stems with the through holes.
Public/Granted literature
- US20160172263A1 METHOD AND STRUCTURE FOR WAFER-LEVEL PACKAGING Public/Granted day:2016-06-16
Information query
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