Invention Grant
- Patent Title: Etch stop layer in integrated circuits
- Patent Title (中): 集成电路中的蚀刻停止层
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Application No.: US14689929Application Date: 2015-04-17
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Publication No.: US09437484B2Publication Date: 2016-09-06
- Inventor: Shiu-Ko JangJian , Tsung-Hsuan Hong , Chun Che Lin , Chih-Nan Wu
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: H01L21/70
- IPC: H01L21/70 ; H01L21/768 ; H01L23/522

Abstract:
An integrated circuit structure includes a dielectric layer and an etch stop layer. The etch stop layer includes a first sub layer including a metal nitride over the first dielectric layer, and a second sub layer overlying or underlying the first sub layer. The second sub layer includes a metal compound comprising an element selected from carbon and oxygen, and is in contact with the first sub layer.
Public/Granted literature
- US20160111325A1 ETCH STOP LAYER IN INTEGRATED CIRCUITS Public/Granted day:2016-04-21
Information query
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