Invention Grant
- Patent Title: Method for fabricating an inter dielectric layer in semiconductor device
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Application No.: US14059756Application Date: 2013-10-22
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Publication No.: US09437423B2Publication Date: 2016-09-06
- Inventor: Byung Soo Eun
- Applicant: SK hynix Inc.
- Applicant Address: KR Icheon-Si
- Assignee: SK hynix Inc.
- Current Assignee: SK hynix Inc.
- Current Assignee Address: KR Icheon-Si
- Agency: Marshall, Gerstein & Borun LLP
- Priority: KR10-2007-0064760 20070628
- Main IPC: H01L21/336
- IPC: H01L21/336 ; H01L21/02 ; H01L21/768 ; H01L27/108 ; H01L21/306

Abstract:
In a method for fabricating an inter dielectric layer in semiconductor device, a primary liner HDP oxide layer is formed by supplying a high density plasma (HDP) deposition source to a bit line stack formed on a semiconductor substrate. A high density plasma (HDP) deposition source is supplied to the bit line stack to form a primary liner HDP oxide layer. The primary liner HDP oxide layer is etched to a predetermined depth to form a secondary liner HDP oxide layer. An interlayer dielectric layer is formed to fill the areas defined by the bit line stack where the secondary liner HDP oxide layer is located.
Public/Granted literature
- US20140045325A1 METHOD FOR FABRICATING AN INTER DIELECTRIC LAYER IN SEMICONDUCTOR DEVICE Public/Granted day:2014-02-13
Information query
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