Invention Grant
US09437296B2 Three-dimensional resistive memory device with adjustable voltage biasing
有权
具有可调电压偏置的三维电阻式存储器件
- Patent Title: Three-dimensional resistive memory device with adjustable voltage biasing
- Patent Title (中): 具有可调电压偏置的三维电阻式存储器件
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Application No.: US14305371Application Date: 2014-06-16
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Publication No.: US09437296B2Publication Date: 2016-09-06
- Inventor: Hiroshi Kanno , Takayuki Tsukamoto , Takamasa Okawa , Atsushi Yoshida
- Applicant: Kabushiki Kaisha Toshiba
- Applicant Address: JP Minato-ku
- Assignee: KABUSHIKI KAISHA TOSHIBA
- Current Assignee: KABUSHIKI KAISHA TOSHIBA
- Current Assignee Address: JP Minato-ku
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Main IPC: G11C13/00
- IPC: G11C13/00 ; H01L27/24

Abstract:
A semiconductor memory device according to an embodiment includes a memory cell array and a control circuit. The memory cell array includes: a plurality of first conductive layers that are stacked; a memory layer provided on a side surface of the plurality of the first conductive layers; and a second conductive layer that contacts the side surface of the plurality of the first conductive layers via the memory layer. A thickness of the first conductive layer disposed at the first position is larger than a thickness of the first conductive layer disposed at the second position. The control circuit is configured to apply a first voltage to a selected first conductive layer. The control circuit changes a value of the first voltage based on a position of the selected first conductive layer.
Public/Granted literature
- US20150221368A1 SEMICONDUCTOR MEMORY DEVICE Public/Granted day:2015-08-06
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