Invention Grant
US09412298B2 Latch circuit of display apparatus, display apparatus, and electronic equipment
有权
显示装置,显示装置和电子设备的锁存电路
- Patent Title: Latch circuit of display apparatus, display apparatus, and electronic equipment
- Patent Title (中): 显示装置,显示装置和电子设备的锁存电路
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Application No.: US14175437Application Date: 2014-02-07
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Publication No.: US09412298B2Publication Date: 2016-08-09
- Inventor: Takeshi Nomura
- Applicant: SEIKO EPSON CORPORATION
- Applicant Address: JP Tokyo
- Assignee: SEIKO EPSON CORPORATION
- Current Assignee: SEIKO EPSON CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: Oliff PLC
- Priority: JP2013-059558 20130322
- Main IPC: G09G5/00
- IPC: G09G5/00 ; G09G3/32 ; G09G3/20

Abstract:
A latch circuit for outputting data for M pixels present in one line on a display panel in a time-division manner for each pixel, in order to drive each pixel from among the M pixels based on N-bit data, includes M×N 1-bit latch circuits in which N 1-bit latch circuits are arranged in the column direction Y and M 1-bit latch circuits are arranged in the row direction X, each circuit latching 1-bit data. Each 1-bit latch circuit includes a data latch unit circuit that latches data corresponding to any one bit of the N bits at different timings for each row, a line latch unit circuit that simultaneously latches data from the data latch unit circuit in each row, and an output enable element that outputs data from the line latch unit circuit based on an enable signal for selecting any one column.
Public/Granted literature
- US20140285405A1 LATCH CIRCUIT OF DISPLAY APPARATUS, DISPLAY APPARATUS, AND ELECTRONIC EQUIPMENT Public/Granted day:2014-09-25
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