Invention Grant
- Patent Title: Tiled cache invalidation
- Patent Title (中): 平铺缓存无效
-
Application No.: US14016847Application Date: 2013-09-03
-
Publication No.: US09411596B2Publication Date: 2016-08-09
- Inventor: Ziyad S. Hakura , Emmett M. Kilgariff
- Applicant: NVIDIA Corporation
- Applicant Address: US CA Santa Clara
- Assignee: NVIDIA Corporation
- Current Assignee: NVIDIA Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Artegis Law Group, LLP
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F9/38 ; G06T15/00 ; G06T15/40 ; G06T1/20 ; G06T1/60 ; G09G5/395 ; G09G5/00 ; G06T15/50 ; G06F12/08 ; G06F9/44 ; G06T15/80

Abstract:
One embodiment of the present invention sets forth a graphics subsystem. The graphics subsystem includes a first tiling unit associated with a first set of raster tiles and a crossbar unit. The crossbar unit is configured to transmit a first set of primitives to the first tiling unit and to transmit a first cache invalidate command to the first tiling unit. The first tiling unit is configured to determine that a second bounding box associated with primitives included in the first set of primitives overlaps a first cache tile and that the first bounding box overlaps the first cache tile. The first tiling unit is further configured to transmit the primitives and the first cache invalidate command to a first screen-space pipeline associated with the first tiling unit for processing. The screen-space pipeline processes the cache invalidate command to invalidate cache lines specified by the cache invalidate command.
Public/Granted literature
- US20140122812A1 TILED CACHE INVALIDATION Public/Granted day:2014-05-01
Information query