Invention Grant
US09406618B2 Die-stacking using through-silicon vias on bumpless build-up layer substrates including embedded-dice, and processes of forming same
有权
在包括嵌入骰子的无扰性积聚层基底上使用硅通孔进行芯片堆叠，以及其形成工艺
- Patent Title: Die-stacking using through-silicon vias on bumpless build-up layer substrates including embedded-dice, and processes of forming same
- Patent Title (中): 在包括嵌入骰子的无扰性积聚层基底上使用硅通孔进行芯片堆叠，以及其形成工艺
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Application No.: US14305439Application Date: 2014-06-16
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Publication No.: US09406618B2Publication Date: 2016-08-02
- Inventor: John S. Guzek , Ravi K. Nalla , Javier Solo Gonzalez , Drew Delaney , Suresh Pothukuchi , Mohit Mamodia , Edward Zarbock , Johanna M. Swan
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Winkle, PLLC
- Main IPC: H01L23/538
- IPC: H01L23/538 ; H01L23/498 ; H01L23/48 ; H01L23/00 ; H01L25/03 ; H01L25/065 ; H01L25/18
Abstract:
An apparatus includes a coreless substrate with a through-silicon via (TSV) embedded die that is integral to the coreless substrate. The apparatus includes a subsequent die that is coupled to the TSV die and that is disposed above the coreless substrate.
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