A latch circuit may include first to fourth storage nodes; first to fourth transistor pairs, each including a PMOS transistor and an NMOS transistor connected in series through a corresponding one of the first to fourth storage nodes, wherein each of the first to fourth storage nodes is connected to a gate of an NMOS transistor of a transistor pair in a previous stage and a gate of a PMOS transistor of a transistor pair in a next stage; a first connection unit suitable for connecting a data bus with a Kth storage node of the first to fourth storage nodes when read and write operations are performed, wherein K is an integer from 1 to 4; and second connection units suitable for connecting the data bus with one or more of the first to fourth storage nodes, except for the Kth storage node, when the write operation is performed.