Invention Grant
- Patent Title: Input-output buffer circuit with a gate bias generator
- Patent Title (中): 具有栅极偏置发生器的输入输出缓冲电路
-
Application No.: US14058117Application Date: 2013-10-18
-
Publication No.: US09385718B1Publication Date: 2016-07-05
- Inventor: Jun Liu , Yanzhong Xu , Bonnie I. Wang , Jeffrey T. Watt
- Applicant: Altera Corporation
- Applicant Address: US CA San Jose
- Assignee: Altera Corporation
- Current Assignee: Altera Corporation
- Current Assignee Address: US CA San Jose
- Main IPC: H03K19/00
- IPC: H03K19/00 ; H03K19/0175 ; H03K19/017
Abstract:
An integrated circuit is disclosed. The integrated circuit includes an input-output (IO) buffer circuit. The IO buffer circuit further includes first and second transistors coupled in series. The first transistor receives an input signal and the second transistor receives a pulsed voltage signal. Furthermore, a method to operate the IO buffer circuit is also disclosed.
Public/Granted literature
- US1233614A Soldering-iron. Public/Granted day:1917-07-17
Information query
