Invention Grant
US09385083B1 Wafer-level die to package and die to die interconnects suspended over integrated heat sinks
有权
晶圆级芯片封装和裸芯片连接在一起散布在散热片上
- Patent Title: Wafer-level die to package and die to die interconnects suspended over integrated heat sinks
- Patent Title (中): 晶圆级芯片封装和裸芯片连接在一起散布在散热片上
-
Application No.: US14720619Application Date: 2015-05-22
-
Publication No.: US09385083B1Publication Date: 2016-07-05
- Inventor: Florian G. Herrault , Melanie S. Yajima , Alexandros Margomenos , Miroslav Micovic
- Applicant: HRL Laboratories, LLC
- Applicant Address: US CA Malibu
- Assignee: HRL Laboratories, LLC
- Current Assignee: HRL Laboratories, LLC
- Current Assignee Address: US CA Malibu
- Agency: Ladas & Parry
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L23/10 ; H01L23/528 ; H01L23/36 ; H01L21/768 ; H01L23/532 ; H05K7/20

Abstract:
An interconnect for electrically coupling pads formed on adjacent chips or on packaging material adjacent the chips, with an electrically conductive heat sink being disposed between the pads, the interconnect comprising a metallic membrane layer disposed between two adjacent pads and disposed or bridging over the electrically conductive heat sink so as to avoid making electrical contact with the electrically conductive heat sink. An electroplated metallic layer is disposed on the metallic membrane layer. Fabrication of interconnect permits multiple interconnects to be formed in parallel using fabrication techniques compatible with wafer level fabrication of the interconnects. The interconnects preferably follow a smooth curve to electrically connect adjacent pads and following that smooth curve they bridge over the intervening electrically conductive heat sink material in a predictable fashion.
Information query
IPC分类: