Invention Grant
- Patent Title: Formal verification of booth multipliers
- Patent Title (中): 展位乘数正式验证
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Application No.: US14019365Application Date: 2013-09-05
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Publication No.: US09384167B2Publication Date: 2016-07-05
- Inventor: Michael L. Case
- Applicant: Calypto Design Systems, Inc.
- Applicant Address: US OR Wilsonville
- Assignee: Mentor Graphics Corporation
- Current Assignee: Mentor Graphics Corporation
- Current Assignee Address: US OR Wilsonville
- Agency: Klarquist Sparkman, LLP
- Main IPC: G06F7/52
- IPC: G06F7/52 ; G06F17/10 ; G06F17/50 ; G06F7/533

Abstract:
Disclosed below are representative embodiments of methods, apparatus, and systems for performing formal verification. For example, certain embodiments can be used to formally verify a Booth multiplier. For instance, in one example embodiment, a specification of a Booth multiplier circuit is received; an initial model checking operation is performed for a smaller version of the Booth multiplier circuit; a series of subsequent model checking operations are performed for versions of the Booth multiplier circuit that are incrementally larger than the smaller version of the Booth multiplier circuit, wherein, for each incrementally larger Booth multiplier circuit, two or more model checking operations are performed, the two or more model checking operations representing decomposed proof obligations for showing; and a verification result of the Booth multiplier circuit is output.
Public/Granted literature
- US20140067897A1 FORMAL VERIFICATION OF BOOTH MULTIPLIERS Public/Granted day:2014-03-06
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