Invention Grant
- Patent Title: Method for manufacturing semiconductor memory device and semiconductor memory device
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Application No.: US14748335Application Date: 2015-06-24
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Publication No.: US09362500B2Publication Date: 2016-06-07
- Inventor: Masaki Yamato , Takeshi Yamaguchi , Shigeki Kobayashi
- Applicant: Kabushiki Kaisha Toshiba
- Applicant Address: JP Minato-ku
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Minato-ku
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Main IPC: H01L45/00
- IPC: H01L45/00 ; H01L27/24

Abstract:
According to one embodiment, a manufacturing method of a semiconductor memory device includes forming a stacked body in which word line material layers and insulating layers are alternately stacked on a base layer. The method includes forming first holes on the stacked body so as to be arranged in a first direction and in a second direction that intersects with the first direction. The method includes forming resistance-change films on inner walls of the first holes, forming bit lines inside the resistance-change films in the first holes, and dividing the stacked body in the first direction by forming second holes so that a portion in the stacked body adjacent to the resistance-change films in the second direction. The method includes forming inter-bit line insulating films in the second holes.
Public/Granted literature
- US20150295174A1 METHOD FOR MANUFACTURING SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY DEVICE Public/Granted day:2015-10-15
Information query
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