A power integrated device includes a drift region disposed in a substrate, a source region disposed in the substrate spaced apart from the drift region, a drain region disposed in the drift region, a gate insulation layer and a gate electrode sequentially stacked on the substrate between the source region and the drift region, a trench isolation layer disposed in the drift region adjacent to a side of the drain region, and a deep trench field insulation layer disposed in the drift region adjacent to another side of the drain region, wherein a vertical height of the deep trench field insulation layer is greater than a width of the deep trench field insulation layer.