Invention Grant
US09362282B1 High-K gate dielectric and metal gate conductor stack for planar field effect transistors formed on type III-V semiconductor material and silicon germanium semiconductor material
有权
用于在III-V族半导体材料和硅锗半导体材料上形成的平面场效应晶体管的高K栅极电介质和金属栅极导体堆叠
- Patent Title: High-K gate dielectric and metal gate conductor stack for planar field effect transistors formed on type III-V semiconductor material and silicon germanium semiconductor material
- Patent Title (中): 用于在III-V族半导体材料和硅锗半导体材料上形成的平面场效应晶体管的高K栅极电介质和金属栅极导体堆叠
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Application No.: US14828225Application Date: 2015-08-17
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Publication No.: US09362282B1Publication Date: 2016-06-07
- Inventor: Takashi Ando , Martin M. Frank , Pranita Kerber , Vijay Narayanan
- Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agency: Tutunjian & Bitetto, P.C.
- Agent Vazken Alexanian
- Main IPC: H01L27/092
- IPC: H01L27/092 ; H01L29/49 ; H01L29/51 ; H01L21/285 ; H01L29/40 ; H01L29/66 ; H01L21/28 ; H01L21/8258 ; H01L29/20 ; H01L29/16
Abstract:
An electrical device that includes a substrate including a first region of a type III-V semiconductor material and a second region of a type IV germanium containing semiconductor material. An n-type planar FET is present in the first region of the substrate. A p-type planar FET is present in a second region of the substrate. A gate structure for each of the n-type planar FET and the p-type planar FET includes a metal containing layer including at least one of titanium and aluminum atop a high-k gate dielectric. An effective work function of the gate structure for both the n-type and p-type planar FETs is a less than a mid gap of silicon.
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