Invention Grant
US09331039B2 Semiconductor device including a buffer layer structure for reducing stress
有权
包括用于减轻应力的缓冲层结构的半导体器件
- Patent Title: Semiconductor device including a buffer layer structure for reducing stress
- Patent Title (中): 包括用于减轻应力的缓冲层结构的半导体器件
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Application No.: US14746183Application Date: 2015-06-22
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Publication No.: US09331039B2Publication Date: 2016-05-03
- Inventor: Takeshi Yuzawa , Masatoshi Tagaki
- Applicant: SEIKO EPSON CORPORATION
- Applicant Address: JP Tokyo
- Assignee: SEIKO EPSON CORPORATION
- Current Assignee: SEIKO EPSON CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: Oliff PLC
- Priority: JP2006-128360 20060502
- Main IPC: H01L29/40
- IPC: H01L29/40 ; H01L21/44 ; H01L23/00 ; H01L23/522 ; H01L23/498 ; H01L23/48 ; H01L23/528 ; H01L23/532
Abstract:
A semiconductor device includes a semiconductor chip, wiring that is included in the semiconductor chip and has a coupling part between parts with different widths, a pad being formed above the wiring and in a position overlapping the coupling part, a bump being formed on the pad, a buffer layer being formed in a position between the coupling part and the pad so as to cover the entire couple part, and inorganic insulating layers being formed between the wiring and the buffer layer and between the buffer layer and the pad, respectively. The buffer layer is made of a material other than resin and softer than the inorganic insulating layer.
Public/Granted literature
- US20150287690A1 SEMICONDUCTOR DEVICE INCLUDING A BUFFER LAYER STRUCTURE FOR REDUCING STRESS Public/Granted day:2015-10-08
Information query
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