Invention Grant
- Patent Title: Automated hybrid metrology for semiconductor device fabrication
- Patent Title (中): 用于半导体器件制造的自动混合测量
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Application No.: US13419286Application Date: 2012-03-13
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Publication No.: US09330985B2Publication Date: 2016-05-03
- Inventor: Alok Vaid , Ned R. Saleh , Matthew J. Sendelbach , Narender N. Rana
- Applicant: Alok Vaid , Ned R. Saleh , Matthew J. Sendelbach , Narender N. Rana
- Applicant Address: KY Grand Cayman US NY Armonk
- Assignee: GLOBALFOUNDRIES, INC.,INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: GLOBALFOUNDRIES, INC.,INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: KY Grand Cayman US NY Armonk
- Agency: Ingrassia Fisher & Lorenz, P.C.
- Main IPC: G06F19/00
- IPC: G06F19/00 ; H01L21/66 ; G03F7/20

Abstract:
Methods and systems are provided for fabricating and measuring features of a semiconductor device structure. An exemplary method of fabricating a semiconductor device structure involves fabricating a feature of the semiconductor device structure on a wafer of semiconductor material, determining a hybrid recipe for measuring the feature, configuring a plurality of metrology tools to implement the hybrid recipe, and obtaining a hybrid measurement of the feature in accordance with the hybrid recipe.
Public/Granted literature
- US20130245806A1 AUTOMATED HYBRID METROLOGY FOR SEMICONDUCTOR DEVICE FABRICATION Public/Granted day:2013-09-19
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