Automated testing system and method of testing memory devices with distributed processing operations. A redundancy analysis system includes multiple test site processors (TSPs) respectively coupled to multiple devices under test (DUTs). Each TSP is installed with a redundancy analyzer configured to analyzing redundancy data returned from a respective (DUT). Each TSP may be coupled with a respective fail engine for returning the redundancy data from the corresponding DUT. A main TSP of the multiple TSPs is configured to control testing routine over the multiple DUTs and process failure related data from the DUTs. The main TSP may direct the RAs distributed in the multiple TSPs to execute the redundancy analyzers in parallel.