Invention Grant
US09281025B2 Write/read priority blocking scheme using parallel static address decode path
有权
使用并行静态地址解码路径的写/读优先级阻塞方案
- Patent Title: Write/read priority blocking scheme using parallel static address decode path
- Patent Title (中): 使用并行静态地址解码路径的写/读优先级阻塞方案
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Application No.: US14501078Application Date: 2014-09-30
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Publication No.: US09281025B2Publication Date: 2016-03-08
- Inventor: Paul A. Bunce , Yuen H. Chan , John D. Davis , Diana M. Henderson
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Cantor Colburn LLP
- Agent Margaret McNamara
- Main IPC: G11C7/10
- IPC: G11C7/10 ; G11C8/10 ; G11C8/16

Abstract:
A method of implementing a write block read function for a memory device includes configuring a dynamic read address decoder to receive static read address bits as inputs thereto and to generate an output used to implement a read operation of a memory location corresponding to the read address bits; configuring a dynamic write address decoder to receive static write address bits as inputs thereto and to generate an output used to implement a write operation of a memory location corresponding to the write address bits; and configuring a static write address decoder, in parallel with the dynamic write address decoder, to receive a portion of the static write address bits as inputs thereto, and coupling the static write address decoder to the dynamic read address decoder so as to block the read operation upon an address conflict with the write operation.
Public/Granted literature
- US20150302908A1 WRITE/READ PRIORITY BLOCKING SCHEME USING PARALLEL STATIC ADDRESS DECODE PATH Public/Granted day:2015-10-22
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