Invention Grant
- Patent Title: Generating a wafer inspection process using bit failures and virtual inspection
- Patent Title (中): 使用位故障和虚拟检查生成晶圆检查过程
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Application No.: US13743074Application Date: 2013-01-16
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Publication No.: US09277186B2Publication Date: 2016-03-01
- Inventor: Poh Boon Yong , George Simon , Yuezhong Du
- Applicant: KLA-Tencor Corporation
- Applicant Address: US CA Milpitas
- Assignee: KLA-Tencor Corp.
- Current Assignee: KLA-Tencor Corp.
- Current Assignee Address: US CA Milpitas
- Agent Ann Marie Mewherter
- Main IPC: H04N7/18
- IPC: H04N7/18 ; H01L21/66

Abstract:
Methods and systems for generating a wafer inspection process are provided. One method includes storing output of detector(s) of an inspection system during scanning of a wafer regardless of whether the output corresponds to defects detected on the wafer and separating physical locations on the wafer that correspond to bit failures detected by testing of the wafer into a first portion of the physical locations at which the defects were not detected and a second portion of the physical locations at which the defects were detected. In addition, the method includes applying defect detection method(s) to the stored output corresponding to the first portion of the physical locations to detect defects at the first portion of the physical locations and generating a wafer inspection process based on the defects detected by the defect detection method(s) at the first portion of the physical locations.
Public/Granted literature
- US20130182101A1 Generating a Wafer Inspection Process Using Bit Failures and Virtual Inspection Public/Granted day:2013-07-18
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