Invention Grant
- Patent Title: Vertical semiconductor devices including superlattice punch through stop layer and related methods
- Patent Title (中): 垂直半导体器件包括超晶格穿通止动层及相关方法
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Application No.: US14550244Application Date: 2014-11-21
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Publication No.: US09275996B2Publication Date: 2016-03-01
- Inventor: Robert Mears , Hideki Takeuchi , Erwin Trautmann
- Applicant: MEARS Technologies, Inc.
- Applicant Address: US MA Wellesley Hills
- Assignee: MEARS TECHNOLOGIES, INC.
- Current Assignee: MEARS TECHNOLOGIES, INC.
- Current Assignee Address: US MA Wellesley Hills
- Agency: Allen, Dyer, Doppelt, Milbrath & Gilchrist, P.A.
- Main IPC: H01L21/336
- IPC: H01L21/336 ; H01L27/088 ; H01L29/66 ; H01L29/78 ; H01L29/10 ; H01L21/324 ; H01L21/8234 ; H01L29/15 ; H01L29/165

Abstract:
A semiconductor device may include a substrate, and a plurality of fins spaced apart on the substrate. Each of the fins may include a lower semiconductor fin portion extending vertically upward from the substrate, and at least one superlattice punch-through layer on the lower fin portion. The superlattice punch-through layer may include a plurality of stacked groups of layers, with each group of layers of the superlattice punch-through layer comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Each fin may also include an upper semiconductor fin portion on the at least one superlattice punch-through layer and extending vertically upward therefrom. The semiconductor device may also include source and drain regions at opposing ends of the fins, and a gate overlying the fins.
Public/Granted literature
- US20150144877A1 VERTICAL SEMICONDUCTOR DEVICES INCLUDING SUPERLATTICE PUNCH THROUGH STOP LAYER AND RELATED METHODS Public/Granted day:2015-05-28
Information query
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