Invention Grant
- Patent Title: Method of manufacturing semiconductor device and semiconductor device
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Application No.: US14259842Application Date: 2014-04-23
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Publication No.: US09275945B2Publication Date: 2016-03-01
- Inventor: Koichi Kanemoto
- Applicant: RENESAS ELECTRONICS CORPORATION
- Applicant Address: JP Tokyo
- Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: Mattingly & Malur, PC
- Priority: JP2013-099833 20130510
- Main IPC: H01L21/44
- IPC: H01L21/44 ; H01L23/495 ; H01L23/00 ; H01L23/544 ; H01L25/065 ; H01L23/49 ; H01L21/66
Abstract:
Reliability of a semiconductor device is improved. A method of manufacturing a semiconductor device includes a step of arranging a plurality of semiconductor chips next to each other over a chip mounting surface of a die pad. Further, the method of manufacturing a semiconductor device includes a step of electrically coupling the semiconductor chip and the semiconductor chip via a wire. In this regard, a pad (chip-to-chip connection pad) of the semiconductor chip on a second bonding side in the step of coupling the wire is provided such that it is distantly located from a peripheral portion of a surface of the semiconductor chip.
Public/Granted literature
- US20140332942A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE Public/Granted day:2014-11-13
Information query
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