Invention Grant
- Patent Title: Semiconductor apparatus and stacked semiconductor apparatus for checking formation and connection of through silicon via
- Patent Title (中): 用于检查硅通孔的形成和连接的半导体装置和堆叠半导体装置
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Application No.: US14216265Application Date: 2014-03-17
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Publication No.: US09275920B2Publication Date: 2016-03-01
- Inventor: Chun Seok Jeong , Jae Jin Lee
- Applicant: SK hynix Inc.
- Applicant Address: KR Gyeonggi-do
- Assignee: SK Hynix Inc.
- Current Assignee: SK Hynix Inc.
- Current Assignee Address: KR Gyeonggi-do
- Agency: William Park & Associates Ltd.
- Priority: KR10-2011-0063781 20110629
- Main IPC: H01L23/58
- IPC: H01L23/58 ; H01L21/66 ; H01L23/48 ; G01R31/28 ; H01L25/065 ; H01L25/00
Abstract:
A semiconductor apparatus includes a TSV formed to be electrically connected with another chip and a TSV test unit configured to check a capacitance component of the TSV to generate a TSV abnormality signal.
Public/Granted literature
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