Invention Grant
- Patent Title: Method of fabricating a semiconductor interconnect structure
- Patent Title (中): 制造半导体互连结构的方法
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Application No.: US14446063Application Date: 2014-07-29
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Publication No.: US09275900B2Publication Date: 2016-03-01
- Inventor: Chih Wei Lu , Chung-Ju Lee
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater & Matsil, L.L.P.
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L21/768 ; H01L21/321 ; H01L21/3213 ; H01L21/311

Abstract:
A method for forming a semiconductor interconnect structure includes forming a dielectric layer on a substrate and patterning the dielectric layer to form an opening therein. A metal layer fills the opening and covers the dielectric layer. The metal layer is planarized so that it is co-planar with a top of the dielectric layer. A treating process is performed on the metal layer to convert a top surface thereof into a metal oxide layer. A copper-containing layer is then formed over the metal oxide layer and the dielectric layer. The copper-containing layer is etched to form interconnect features, wherein the etching stops at the metal oxide layer and does not etch into the underlying metal layer. A radiation exposure process is thereafter performed on the metal oxide layer to convert it into a non-oxidized metal layer.
Public/Granted literature
- US20140335689A1 Method of Fabricating a Semiconductor Interconnect Structure Public/Granted day:2014-11-13
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