Invention Grant
US09275864B2 Method to form a polysilicon nanocrystal thin film storage bitcell within a high k metal gate platform technology using a gate last process to form transistor gates
有权
在高k金属栅极平台技术中使用栅极最后工艺形成晶体管栅极的方法来形成多晶硅纳米晶体薄膜存储位单元
- Patent Title: Method to form a polysilicon nanocrystal thin film storage bitcell within a high k metal gate platform technology using a gate last process to form transistor gates
- Patent Title (中): 在高k金属栅极平台技术中使用栅极最后工艺形成晶体管栅极的方法来形成多晶硅纳米晶体薄膜存储位单元
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Application No.: US13973433Application Date: 2013-08-22
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Publication No.: US09275864B2Publication Date: 2016-03-01
- Inventor: Asanga H Perera , Sung-Taeg Kang , Jane A Yater , Cheong Min Hong
- Applicant: Freescale Semiconductor, Inc.
- Applicant Address: US TX Austin
- Assignee: FREESCALE SEMICONDUCTOR,INC.
- Current Assignee: FREESCALE SEMICONDUCTOR,INC.
- Current Assignee Address: US TX Austin
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L21/28 ; H01L29/423 ; H01L27/115 ; H01L29/66 ; H01L29/788
Abstract:
A process integration is disclosed for fabricating non-volatile memory (NVM) cells (105-109, 113-115) on a first flash cell substrate area (111) which are encapsulated in one or more planar dielectric layers (116) prior to forming an elevated substrate (117) on a second CMOS transistor area (112) on which high-k metal gate electrodes (119-120, 122-126, 132, 134) are formed using a gate-last HKMG CMOS process flow without interfering with the operation or reliability of the NVM cells.
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