A semiconductor memory device comprises: first lines; second lines; memory cells; a first and second select gate transistor; and a control circuit. The first lines are arranged with a certain pitch in a first direction perpendicular to a substrate and are extending in a second direction parallel to the substrate. The second lines are arranged with a certain pitch in the second direction, are extending in the first direction, and intersect the plurality of first lines. The memory cells are disposed at intersections of the first lines and the second lines. The first and second select gate transistors each include a first or second channel line that are connected to a lower end or an upper end of the second line and a first or second gate line. The control circuit controls the first and second select gate transistors independently.