Invention Grant
US09275721B2 Split bit line architecture circuits and methods for memory devices
有权
分离位线架构电路和存储器件的方法
- Patent Title: Split bit line architecture circuits and methods for memory devices
- Patent Title (中): 分离位线架构电路和存储器件的方法
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Application No.: US12847647Application Date: 2010-07-30
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Publication No.: US09275721B2Publication Date: 2016-03-01
- Inventor: Yi-Tzu Chen , Bin-Hau Lo , Tsai-Hsin Lai , Pey-Huey Chen , Hau-Tai Shieh
- Applicant: Yi-Tzu Chen , Bin-Hau Lo , Tsai-Hsin Lai , Pey-Huey Chen , Hau-Tai Shieh
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater & Matsil, L.L.P.
- Main IPC: G11C11/40
- IPC: G11C11/40 ; G11C11/4097 ; G11C5/06

Abstract:
Apparatus and methods for providing a high density memory array with reduced read access time are disclosed. Multiple split bit lines are arranged along columns of adjacent memory bit cells. A multiple input sense amplifier is coupled to the multiple split bit lines. The loading on the multiple split bit line is reduced, and the corresponding read speed of the memory array is enhanced over the prior art. The sense amplifier and the memory bit cells have a common cell pitch layout height so that no silicon area penalty arises due to the use of the multiple split bit lines and sense amplifiers. Increased memory array efficiency is achieved.
Public/Granted literature
- US20120026818A1 Split Bit Line Architecture Circuits and Methods for Memory Devices Public/Granted day:2012-02-02
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