Invention Grant
US09275708B2 Row address decoding block for non-volatile memories and methods for decoding pre-decoded address information
有权
用于非易失性存储器的行地址解码块以及用于解码预解码地址信息的方法
- Patent Title: Row address decoding block for non-volatile memories and methods for decoding pre-decoded address information
- Patent Title (中): 用于非易失性存储器的行地址解码块以及用于解码预解码地址信息的方法
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Application No.: US14180060Application Date: 2014-02-13
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Publication No.: US09275708B2Publication Date: 2016-03-01
- Inventor: Marco Giovanni Fontana , Giuseppe Sciascia , Giovanni Bolognini
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Dorsey & Whitney LLP
- Main IPC: G11C8/10
- IPC: G11C8/10 ; G11C16/08
Abstract:
Decoding blocks, memories, and methods for decoding pre-decoded address information are disclosed. One such decoding block includes a first latch and voltage shift circuit configured to receive first pre-decoded address information at first voltage levels and further configured to latch the first pre-decoded address information and shift the voltage levels of the same to second voltage levels. An address decoder includes a second latch and voltage shift circuit configured to receive second pre-decoded address information at the first voltage levels and latch and shift the voltage levels of the same to the second voltage levels. The address decoder is further configured to select control gates of the memory cells of the memory based at least in part on the first and second pre-decoded address information.
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