Invention Grant
US09275002B2 Tile-based processor architecture model for high-efficiency embedded homogeneous multicore platforms 有权
用于高效嵌入式均匀多核平台的基于平铺的处理器架构模型

  • Patent Title: Tile-based processor architecture model for high-efficiency embedded homogeneous multicore platforms
  • Patent Title (中): 用于高效嵌入式均匀多核平台的基于平铺的处理器架构模型
  • Application No.: US13576219
    Application Date: 2011-01-31
  • Publication No.: US09275002B2
    Publication Date: 2016-03-01
  • Inventor: Philippe ManetBertrand Rousseau
  • Applicant: Philippe ManetBertrand Rousseau
  • Agency: Young & Thompson
  • Priority: GB1001621.0 20100201
  • International Application: PCT/EP2011/051297 WO 20110131
  • International Announcement: WO2011/092323 WO 20110804
  • Main IPC: G06F15/76
  • IPC: G06F15/76 G06F15/173 G06F9/38 G06F15/78
Tile-based processor architecture model for high-efficiency embedded homogeneous multicore platforms
Abstract:
The present invention relates to a processor which comprises processing elements that execute instructions in parallel and are connected together with point-to-point communication links called data communication links (DCL). The instructions use DCLs to communicate data between them. In order to realize those communications, they specify the DCLs from which they take their operands, and the DCLs to which they write their results. The DCLs allow the instructions to synchronize their executions and to explicitly manage the data they manipulate. Communications are explicit and are used to realize the storage of temporary variables, which is decoupled from the storage of long-living variables.
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