Invention Grant
- Patent Title: Sideband logic for monitoring PCIe headers
- Patent Title (中): 用于监视PCIe标头的边带逻辑
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Application No.: US14280906Application Date: 2014-05-19
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Publication No.: US09274915B2Publication Date: 2016-03-01
- Inventor: Brian Lessard , Robert E. Ward
- Applicant: LSI CORPORATION
- Applicant Address: SG Singapore
- Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
- Current Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
- Current Assignee Address: SG Singapore
- Main IPC: G06F11/00
- IPC: G06F11/00 ; G06F11/30 ; G06F13/24 ; G06F13/42
Abstract:
Disclosed is a system and method for monitoring PCIe packets between clock domains. An interrupt is set to a root complex or external hardware based on the detection of malformed, and illegal, packets.
Public/Granted literature
- US20150331773A1 SIDEBAND LOGIC FOR MONITORING PCIe HEADERS Public/Granted day:2015-11-19
Information query
