Invention Grant
US09274891B2 Decoding method, memory storage device, and memory controlling circuit unit
有权
解码方法,存储器存储装置和存储器控制电路单元
- Patent Title: Decoding method, memory storage device, and memory controlling circuit unit
- Patent Title (中): 解码方法,存储器存储装置和存储器控制电路单元
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Application No.: US14190103Application Date: 2014-02-26
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Publication No.: US09274891B2Publication Date: 2016-03-01
- Inventor: Wei Lin , Shao-Wei Yen , Yu-Hsiang Lin , Kuo-Hsin Lai
- Applicant: PHISON ELECTRONICS CORP.
- Applicant Address: TW Miaoli
- Assignee: PHISON ELECTRONICS CORP.
- Current Assignee: PHISON ELECTRONICS CORP.
- Current Assignee Address: TW Miaoli
- Agency: Jianq Chyun IP Office
- Priority: TW102149310A 20131231
- Main IPC: G06F11/10
- IPC: G06F11/10 ; H03M13/11 ; H03M13/37

Abstract:
A decoding method, a memory storage device and a memory controlling circuit unit are provided. The decoding method includes: reading at least one memory cell according to a first read voltage to obtain at least one first verification bit; executing a hard bit mode decoding procedure according to the first verification bit, and determining whether a first valid codeword is generated by the hard bit mode decoding procedure; if the first valid codeword is not generated by the hard bit mode decoding procedure, obtaining storage information of the memory cell; deciding a voltage number according to the storage information; reading the memory cell according to second read voltages matching the voltage number to obtain second verification bits; and executing a soft bit mode decoding procedure according to the second verification bits. Accordingly, the speed of decoding is increased.
Public/Granted literature
- US20150186212A1 DECODING METHOD, MEMORY STORAGE DEVICE, AND MEMORY CONTROLLING CIRCUIT UNIT Public/Granted day:2015-07-02
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