Invention Grant
- Patent Title: Regulator circuit
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Application No.: US14563790Application Date: 2014-12-08
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Publication No.: US09274537B2Publication Date: 2016-03-01
- Inventor: Hiromi Notani
- Applicant: RENESAS ELECTRONICS CORPORATION
- Applicant Address: JP Tokyo
- Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: McDermott Will & Emery LLP
- Priority: JP2010-140449 20100621
- Main IPC: G05F1/10
- IPC: G05F1/10 ; G05F1/575

Abstract:
There is provided a regulator circuit capable of increasing the capacity of the output transistor for supplying current, stably generating an internal power supply voltage and adapting to the reduction of a power supply voltage. The regulator circuit includes an output transistor which is supplied with an external power supply voltage and supplies dropped voltage to an internal circuit, a differential amplifier for outputting a gate potential applied to the gate of the output transistor, a reference voltage generating circuit for supplying a reference voltage to the differential amplifier, and a cut-off transistor for turning off the output transistor to stop supplying power to the internal circuit. The output transistor is comprised of a depression NMOS transistor whose threshold voltage is a negative voltage. The regulator circuit further includes substrate potential control means for controlling the substrate potential of the depression NMOS transistor.
Public/Granted literature
- US20150091542A1 REGULATOR CIRCUIT Public/Granted day:2015-04-02
Information query
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