Invention Grant
- Patent Title: Selective test pattern processor
- Patent Title (中): 选择性测试模式处理器
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Application No.: US14055952Application Date: 2013-10-17
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Publication No.: US09274172B2Publication Date: 2016-03-01
- Inventor: Donato O. Forlenza , Orazio P. Forlenza , Michael P. Grace , Bryan J. Robbins
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Cantor Colburn LLP
- Agent Margaret McNamara
- Main IPC: G01R31/3177
- IPC: G01R31/3177 ; G01R31/28 ; G06F11/25 ; G01R31/3183
Abstract:
A method, system, and computer program product to test a semiconductor device are described. The method includes receiving a set of test patterns for testing the semiconductor device and a user selecting a subset of the set of test patterns. The method also includes cataloging a content of pattern files associated with the subset of the set of test patterns to generate a catalog, and processing the catalog to output test data to the semiconductor device.
Public/Granted literature
- US20150113349A1 SELECTIVE TEST PATTERN PROCESSOR Public/Granted day:2015-04-23
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