An analog phase-locked loop, PLL, (100, 200) is disclosed, comprising a voltage controlled oscillator (102, 202); a frequency divider (104, 204) having its input connected to an output of the VCO; a first phase detector (106, 206) arranged to detect a phase difference between an output signal of the frequency divider and a reference frequency signal and provide an output signal based on the phase difference, wherein the detectable phase difference is within one cycle of the reference frequency; a first charge pump (108, 208) connected to an output of the first phase detector and arranged to output a charge per detected phase error based on the output of the first phase detector; and an analog loop filter (110, 210) connected to the first charge pump and arranged to provide a voltage, based on the output of the first charge pump, to the VCO. The PLL further comprises a second phase detector (112, 212, 300, 400, 500) arranged to detect a number of cycles in phase difference between the output signal of the frequency divider and the reference frequency signal and provide an output signal based on the number of cycles in phase difference; and a second charge pump (114, 214, 600, 700) connected to an output of the second phase detector and arranged to provide a charge per detected phase error, based on the output of the second phase detector, to the loop filter. A radio circuit, a communication device and a communication node are also disclosed.